Connect the Dots: Bohr’s Law Standardizes Process-Node IC Density Reference

Create: 04/07/2017 - 14:41
Mark Bohr Intel

When Mark Bohr stands up to talk, it’s good to listen. He recently took the stage to set the record straight regarding semiconductor process nodes, but that was only part of the story: The move to 22-nm FFL technology also has enormous implications for IoT devices.

Of all the IoT dots we talk about, the lowly transistor has to be one of the most overlooked yet fundamentally critical. Yet as fundamental as it is, it is not immune to a bit of marketing and hyperbole regarding transistor density. So much so, that Bohr, senior Intel Fellow and director of process architecture and integration at Intel Corp., took the stage at the recent 2017 Manufacturing Day to discuss it. Bohr took issue with the misapplication of Moore’s Law when it came to naming semiconductor process nodes.

Moore’s Law is more of an observation that the number of transistors on an IC (of a given area) will double every 18 months or so. This has been both an indicator as well as a driver of the semiconductor industry as everyone was compelled to adhere to that schedule and curve.

At the recent Intel Manufacturing Day, Bohr discussed his interpretation of Moore’s Law that refers to a doubling of transistors on a chip with each process generation. As such, each process node is 0.7x smaller than the previous one, giving a linear scaling that gives a doubling of density. This scaling is indicated by the terms 90 nm, 65 nm, 45 nm and 32 nm, referring to a combination of transistor features.

One question that Bohr’s interpretation brings up is: What if the next process node takes longer than a year to reach? Or, more confusingly, and more to Bohr’s point: What if the next process node doesn’t achieve any increase in density at all?  Is it really a process node jump?

For designers of IoT systems and IoT-based solutions, it’s always good to promote their technology as having chips with the latest process node, with its associated increase in transistor density and more functionality per microwatt of power consumed. However, the benefits assume that there is an actual increase in density, that the leakage current has been minimized and that the high manufacturing costs have been contained, or at least aren’t passed on directly to the OEM or consumer.

Not all these are good assumptions, particularly with respect to transistor density and leakage current. The latter is of particular interest to the IoT, but more on that in a minute. First, to Bohr’s sticking point with regard to Moore’s Law, process nodes, density and removing the marketing-induced ambiguity.

Moore’s Marketing

Bohr’s point is that the difficulty of scaling to finer nodes has led some companies to abandon the 0.7x/node rule when naming nodes, applying the new-node nomenclature without increasing transistor density. So much so that node names no longer map to the Moore’s Law curve. This means that different IC vendors can claim the same node, yet have wildly differing transistor densities.

If an IoT provider buys, designs and sells based on assumptions around an IC node specification, and the end customer realizes the difference, they may end up holding the bag for what was effective, but misleading, marketing.

Bohr’s Law?

To avoid this, Bohr came up with a standardized density metric. More accurately, he resurrected an old metric:

0.6

x

NAND2 Tr Count

+

0.4

x

Scan Flip Flop Tr Count

=

# Transistors/mm2

NAND2 Cell Area

Scan Flip Flop Cell Area

 

The metric is based on the transistor density of standard logic cells, with the weightings of 0.6 and 0.4 being used to account for the ratio of small and large cells in different designs.

The formula uses a simple but ubiquitous cell, a 2-input NAND cell, which uses four transistors, and a more-complex scan flip-flop (SFF).

According to Bohr, if every chipmaker gave logic density in terms of millions of transistors/mm2 (MTr/mm2) using this formula, everyone would be on the same page. And there would be no ambiguity, or surprises. 

The caveat is SRAM cell size. With a wide variety of SRAM-to-logic ratios across different ICs, Bohr suggests vendors report SRAM cell size separately, next to the NAND+SFF density metric.

It’s Now Safe to Move IoT to 22 nm

Going back to the cost and current leakage topics mentioned earlier. Due to the high costs and high current leakage associated with advanced nodes, a number of semiconductor companies experts declared 28 nm to be the “sweet spot” for ICs, at least for the past couple of years. Bohr disagrees.

Current leakage occurs even when a device is off, and it increases as the transistor gates get narrower with each process node. This one reason, along with cost, is why 28 nm seemed to be a good spot to start focusing on applications, architectures, interfaces and other innovations, rather than simply driving to the next node. This is especially true for IoT applications, especially those that are battery driven. Many such applications have low duty cycles, so a larger proportion of battery power is “leaked” instead of being used directly.
 

Intel IC transistors

Intel’s ultra-low-power FinFet process reduces current leakage by more than 100x, which is a critical enhancement to battery-driven IoT devices. (Source: Intel Corp.)

However, using its ultra-low-power, FinFet technology, Bohr believes ICs can achieve more than 100x reduction in leakage current, at proven 22- and even 14-nm nodes. And, he indicated it’s cost competitive with other 28/22-nm planar technologies.

If he’s right, the sweet-spot has moved and IoT solution providers can not only start to have confidence in their IC specs, but also that the specs will even improve dramatically, making next-gen solutions a lot more capable, at lower power and cost. 

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Patrick Mannion
Patrick Mannion is an independent writer and content consultant who has been working in, studying, and writing about engineering and technology for over 25 years.

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